1. Technical Field
The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to a thin film transistor (TFT) array substrate for an LCD device and a method for fabricating the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices have recently attracted considerable attention as flat panel display devices. A great deal of research has been conducted on the LCD devices due to their large contrast ratio and superior suitability for gray scale display or moving image display.
Since such LCD devices can have a small thickness, they are utilized in ultra-thin display devices such as wall-mounted televisions. The LCD devices are also utilized in a wide variety of applications, including display devices for notebook computers powered by batteries, private mobile communication terminals, television (TV) sets and aircraft monitors, due to their low weight and considerable small power consumption as compared to cathode-ray tube (CRT) monitors such as Brown tube monitors. For these advantages, the LCD devices have been focused as next-generation display devices.
Such an LCD device generally consists of a thin film transistor (TFT) array substrate, wherein a thin film transistor, a pixel electrode and a storage capacitor are formed on each of pixel regions defined by a gate line and a data line, a color filter layer array substrate on which a color filter layer and a common electrode are formed, and a liquid crystal layer interposed between the TFT array substrate and the color filter layer array substrate. When a voltage is applied to the electrodes, liquid crystal molecules of the liquid crystal layer are rearranged, thereby controlling the amount of light transmitted through the liquid crystal layer. Based on this principle, the LCD device displays an image.
The LCD device is formed with a variety of patterns for operating devices or lines on a substrate. For the formation of such patterns, photolithography is typically used.
The photolithography comprises: coating a photoresist material which is photosensitive to UV light, over a film layer overlying a substrate on which patterns are to be formed; soft-baking the coated photoresist at a relatively high temperature, coating an exposure mask overlying the soft-baked photoresist and exposing the photoresist to light through a pattern formed in the exposure mask; developing and patterning the exposed photoresist, and hard-baking the patterned photoresist at higher temperature; etching the film layer using the patterned photoresist as a mask, and removing the photoresist by a stripping process.
Photolithography is typically conducted 5 to 7 times for a conventional TFT array substrate to form a gate line layer, a gate insulating film, a semiconductor layer, a data line layer, a passivation layer and a pixel electrode on the substrate. An increase in the number of photolithography processes using the photoresist causes a greater chance of process errors and higher material costs. In this end, a number of studies are being made to minimize the use frequency of photolithography, and thus, to achieve an enhancement in productivity.
Hereinafter, a conventional method for forming a TFT array substrate will be described with reference to the accompanying drawings.
FIGS. 1A to 1C are sectional views illustrating a method for fabricating a conventional TFT array substrate.
With reference to FIG. 1A, a low resistance metal material is first deposited on a glass substrate 11. Photolithography is then conducted using a first exposure mask to form a plurality of gate line layers, i.e., a gate line (not shown), a gate electrode 12a and a lower storage electrode 32.
Next, an inorganic insulating material such as a silicon nitride (SiNx) or a silicon oxide (SiOx) is deposited over the entire upper surface of the glass substrate 11 including the gate electrode 12a at high temperature to form a gate insulating film 13. Consecutively, amorphous silicon is deposited on the gate insulating film 13 in such a manner to overlap the gate electrode 12a, and is subjected to photolithography using a second exposure mask, to form a semiconductor layer 14 in the form of an island.
The depositions of the gate insulating film 13 and semiconductor layer 14 are achieved by general plasma enhanced chemical vapor deposition (PECVD). Next, another low resistance metal material is deposited over the entire upper surface of the resulting structure including the semiconductor layer 14 and photolithography is conducted using a third exposure mask to form a data line 15 and a source electrode 15a and a drain electrode 15b. 
The data line intersects with the gate line such that a unit pixel is defined at an intersection of the data line and gate line. Each of the source electrode 15a and a drain electrode 15b is overlapped with an edge of the semiconductor layer 14. The gate electrode 12a, the gate insulating film 13, the semiconductor layer 14 and the source electrode 15a and a drain electrode 15b are laminated together to form a thin film transistor that performs on/off operations for a voltage applied to a unit pixel. The thin film transistor is located at an intersection of the data line and gate line.
Next, an inorganic insulating material selected from the group consisting of a silicon nitride (SiNx) and a silicon oxide (SiOx) or an organic insulating material selected from the group consisting of benzocyclobutene (BCB) and acryl-based resin is deposited over the entire upper surface of the resulting structure including the data line 15 to form a passivation layer 16.
A photosensitive photoresist 19 is coated on the passivation layer 16, and then is subjected to a soft-baking process. The photoresist 19 is selectively exposed to light (e.g., UV) irradiation in a state which a fourth exposure mask 20 having a specific pattern is arranged on the photoresist 19. Next, the photoresist 19 is patterned by removing the exposed photoresist portion using a developing solution, followed by hard-baking. A portion of the passivation layer 16 exposed through the patterned photoresist is then removed to form a contact hole 20. The contact hole 20 is formed through which the drain electrode 15b is exposed.
The photoresist 19 is subjected to stripping using a stripper, after the formation of the contact hole 20 by photolithography using a stepper.
With reference to FIG. 1C, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited over the entire upper surface of the resulting structure including the passivation layer 16, and then is subjected to patterning by photolithography to form a pixel electrode 17 electrically connected with the drain electrode 15b through the contact hole 20. The pixel electrode 17 is formed to overlap the storage electrode 32 to form a storage capacitor. As a result, the fabrication of the TFT array substrate is completed.
However, the above-mentioned conventional TFT array substrate and the above-mentioned conventional method for fabricating the TFT array substrate have various problems as follows.
To form a contact hole in the passivation layer of the conventional TFT array substrate, various processes are required, such as photoresist coating, soft-baking, light exposure, developing, hard-baking and stripping. For this reason, the overall processes become complex, thereby causing an increase in process defects, an increase in processing time, and an increase in fabrication and material costs. As a result, a reduction in productivity occurs.
Either an inorganic insulating material or an organic insulating material may be used to form a passivation layer. However, the use of the inorganic insulating material causes a reduction in an aperture ratio of the resulting LCD device.
Specifically, when an inorganic insulating material having a high dielectric constant of 6 to 8 is used, a parasite capacitance (Cdp) disadvantageously results between a data line and a pixel electrode. The generated parasite capacitance (Cdp) induces source delay, namely, a decrease in data voltage level and vertical crosstalk, namely, a variation luminance due to the source delay. As a result, a degradation in picture quality occurs.
In an attempt to prevent generation of the Cdp, data lines and pixel electrodes are formed to be spaced apart from each other, such that they do not overlap each other. However, since the area of each pixel electrode decreases, there arises another problem of a reduction in an aperture ratio of the resulting LCD device.
Thus, to increase the aperture ratio of the LCD device, based on formation of a pixel electrode having a maximum area, it is indispensable that the pixel electrode and data line overlap each other. For this reason, a passivation layer must have a low dielectric constant. To this end, use of an organic insulating material having a low dielectric constant of 3 to 4 for forming the passivation layer has been suggested.
As is apparent from the above description, use of an organic insulating material for forming the passivation layer involves a coating method such as spin coating or slit coating other than PECVD, in contrast to the use of an inorganic insulating material. The coating methods have the advantages of simplifying the fabrication process, reducing equipment costs, and preventing occurrence of a parasite capacitance (Cdp). However, the passivation layer formed by such a coating method has an increased thickness. Thus, there is a limitation in terms of lightness.
For example, when a passivation layer is formed using an organic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) having a dielectric constant of about 6 to about 8, the passivation layer typically has a thickness of 1500 to 5000 Å. On the other hand, when an organic insulating material such as benzocyclobutene (BCB) or acryl-based resin having a dielectric constant of about 3 to about 4 is used, the passivation layer typically has a thickness of about 3 μm.